1. Field of the Invention
The present invention generally relates to a digital communications device used in a digital communications network, and more particularly to a synchronizing system provided in a digital receiver system and designed to detect distributed frame patterns distributed in a main frame of a transmission signal.
2. Description of the Prior Art
FIG. 1 shows a frame format of a main frame of a transmission signal transferred in a digital communications network. A main frame 1, which consists of n bits, includes first and second sub-frames 2 and 3. Each of the first and second sub-frames 2 and 3 consists of m bits (m&lt;n). The first sub-frame 2 includes a p-bit sub-frame pattern (F1) 2a located at the beginning portion of the first sub-frame 2. The second sub-frame 3 includes a p-bit sub-frame pattern (F2) 2b located at the beginning portion of the second sub-frame 3.
A digital receiver system in a digital communications device detects the sub-frame patterns 2a and 3a from a digital signal received via a transmission line, and separates data 2b contained in the first sub-frame 2 and data 3b contained in the second sub-frame 3 from each other at timings based on the detected sub-frame patterns 2a and 3a.
FIG. 2 is a block diagram of a synchronizing system provided in the digital receiver system. A timing generator (TIMGEN) 11 divides the frequency of an external clock signal CLK and thereby generates various timing signals corresponding to bit allocations in the main frame 1. Examples of the timing signals generated by the timing generator 11 are a separation timing signal for separating the pieces 2b and 3b of data from each other, and sub-frame pattern timing signals FP1 and FP2 for detecting the frame patterns 2a and 3a respectively.
A first frame pattern detector (F1 DET) 12 detects the same pattern as the first sub-frame pattern 2a contained in the first sub-frame 2 in the main frame 1 of data received via the transmission line. More particularly, the first frame pattern detector 12 compares P consecutive bits from the starting (first) bit with the sub-frame pattern (F1) 2a. When the P consecutive bits form the sub-frame pattern 2a, the first sub-frame pattern detector 12 generates a detection signal FP1D. As shown in FIG. 3(a), the detection signal FP1D is a pulse signal that rises each time the sub-frame pattern (F1) 2a is detected.
A second sub-frame pattern detector (F2 DET) 13 detects the same pattern as the second sub-frame pattern 3a contained in the second sub-frame 3 in the main frame 1 of data received via the transmission line More particularly, the second sub-frame pattern detector 13 compares P consecutive bits from the (m+1)th bit with the sub-frame pattern (F2) 3a. When the P consecutive bits form the sub-frame pattern 3a, the second sub-frame pattern detector 13 generates a detection signal FP2D, which is a pulse signal that rises each time the sub-frame pattern (F2) 3a is detected.
A mismatch detector 14 determines whether or not the detection signal FP1D related to the sub-frame pattern 2a is received at the timing of the sub-frame pattern timing signal FP1 generated by the timing generator 11. When the result of the above determination is negative, the mismatch detector 14 determines that the receiver system is out of phase with respect to the first sub-frame 2, and outputs a high-level signal (mismatch detection signal) to a negative-logic OR gate (which corresponds to a positive-logic AND gate) 16. As will be described in detail later, a negative-logic OR gate 18 outputs a high-level signal to a negative-logic OR gate 19 in response to the mismatch detection signal Hence, the OR gate 19 prevents the external clock signal CLK from passing therethrough. That is, the output signal of the OR gate 19 is fixed at the high level. Hence, the timing generator 11 fixes the sub-frame pattern timing signal FP1 at the high level. When the mismatch detector 14 determines that the sub-frame pattern detection signal FP1D is received while the sub-frame pattern timing signal FF1 is fixed at the high level, the mismatch detector 14 generates a low-level signal (match detection signal). It will be noted that the sub-frame pattern detection signal FP1D is received when the sub-frame pattern timing signal FP1 is received if the receiver system is synchronized with the first sub-frame 2.
A mismatch detector 15 determines whether or not the detection signal FP2D related to the sub-frame pattern 3a is received at the timing of the sub-frame pattern timing signal FP2 generated by the timing generator 11. When the result of the above determination is negative, the mismatch detector 15 determines that the receiver system is out of phase with respect to the second sub-frame 3, and outputs a high-level signal (mismatch detection signal) to the negative-logic OR gate 16. Then the negative-logic OR gate 18 outputs the high-level signal to the negative-logic OR gate 19 in response to the mismatch detection signal. Hence, the OR gate 19 prevents the external clock signal CLK from passing therethrough. That is, the output signal of the OR gate 19 is fixed at the high level. Hence, the timing generator 11 fixes the sub-frame pattern timing signal FP2 at the high level. When the mismatch detector 15 determines that the sub-frame pattern detection signal FP2D is received while the frame pattern timing signal FP2 is fixed at the high level, the mismatch detector 15 generates a low-level signal (match detection signal) It will be noted that the sub-frame pattern detection signal FP2D is received when the sub-frame pattern timing signal FP2 is received if the receiver system is synchronized with the second sub-frame 3.
A synchronization protection circuit 17 has an input terminal connected to the OR gates 16 and 18, and an output terminal connected to the OR gate 18. When the unit 17 determines that the match detection signal has been repeatedly received a predetermined number of times, it outputs a low-level output signal to the OR gate 18. Hence, the OR gate 18 allows the low-level signal to pass through the OR gate 18. Until the match detection signal has been received the predetermined number of times, the unit 17 outputs a high-level output signal to the OR gate 18. The high-level output signal of the OR gate 18 is particularly referred to as a clock inhibit signal. It will be seen from the above that the synchronization protection circuit 17 is intended to ensure that the receiver system has been pulled into synchronization with the received data.
A description will now be given of the operation of the synchronizing system with reference to FIG. 3 related to the first sub-frame 2.
As shown in FIG. 3(a), the first sub-frame pattern detector 12 does not detect the frame pattern (F1) 2a at the third n-bit frame period due to data error or the like, and does not generate the sub-frame pattern detection signal FP1D. At this time, the mismatch detector 14 does not receive the sub-frame pattern detection signal FP1D when receiving the sub-frame pattern timing signal FP1. Hence, the mismatch detector 14 outputs the mismatch detection signal to the OR gate 16. In this case, the OR gate 19 prevents the external clock signal CLK from passing therethrough, and hence the timing generator 11 fixes the frame pattern timing signal FP1 at the high level, as shown in FIG. 3(b).
The first sub-frame pattern detector 12 detects the sub-frame pattern (F1) 2a at the fourth frame period as shown in FIG. 3(a). Since the frame pattern timing signal FP1 is maintained at the high level, the mismatch detector 14 outputs the low-level output signal (the match detection signal) to the OR gate 16. At this time, the synchronization protection circuit 17 does not change its output signal and maintains it at the high level. That is, the clock inhibit signal output from the OR gate 18 is still active. When the match detection signal has been received the predetermined number of times, the unit 17 changes the output signal from the high level to the low level. Then, the OR gate 19 starts once again to transfer the external clock signal CLK to the timing generator 11.
In the system processing the distributed sub-frame patterns 2a and 3a, it is required that the frame patterns 2a and 3a should be unique sub-frame patterns which do not occur in the data fields 2b and 3b shown in FIG. 1. A unified sub-frame pattern consisting of the combination of the frame patterns 2a and 3a will be unique and will not occur in the data fields 2b and 3b. However, in the synchronizing system shown in FIG. 2, the sub-frame patterns 2a and 3a are separately detected In this case, there is a possibility that a pseudo sub-frame pattern identical to the sub-frame pattern 2a or 3a may occur in the data field 2b or 3b.
FIG. 4(a) illustrates pseudo sub-frame patterns QFP which are the same as the true sub-frame pattern (F1) 2a. The first sub-frame detector 12 detects not only the true sub-frame pattern 2a but also the pseudo sub-frame pattern QFP. When the first sub-frame detector 12 detects the same pseudo sub-frame pattern as the sub-frame pattern 2a, the mismatch detector 14 generates the mismatch detection signal since the mismatch detector 14 does not receive the sub-frame pattern timing signal FP1 at that time. Hence, it is necessary to mask the sub-frame pattern detection signal FP1D while the sub-frame pattern timing signal FP1 is not being generated, in other words, for the n-bit period. Thereby, as shown in FIG. 4, only the true sub-frame pattern 2a can be detected and the synchronizing system is pulled in synchronization with the received data.
However, if the pseudo sub-frame pattern QFP is detected when the sub-frame pattern timing signal FP1 is generated, the mismatch detector 14 generates the match detection signal. Since the sub-frame pattern detection signal FP1D is masked (prevented from being applied to the mismatch detector 14) for the n-bit period, the true sub-frame pattern 2a is lost. In this manner, the synchronizing (hunting) operation is greatly affected by the pseudo frame pattern QFP, and it takes a long time to detect (hunt) the true sub-frame pattern and pull the receiving system into synchronization with the received data.